CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

Keywords: real numbers, conveying, FPGA, computing performance, adder.

Abstract

The purpose of these studies is to develop an effective structure and internal functional blocks
of a digital computing device an adder, that performs addition and subtraction operations on floatingpoint numbers presented in IEEE Std 754™-2008 format. To improve the characteristics of the adder, the
circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This
allows you to perform addition / subtraction operations on several numbers at the same time, which increases the performance of calculations, and also makes the adder suitable for use in modern synchronous circuits.
Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a
digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experimental testing and phased debugging of the entire device. Experimental studies were performed using EDA
Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An analogue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made
and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor
structure of the adder.
Implementation of arithmetic over the floating-point numbers on programmable logic integrated circuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also
provides the opportunity to solve problems for which there are no ready-made solutions in the form of standard devices presented on the market. The developed adder has a wide scope, since most modern computing
devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to
implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases
where the complex functionality of these devices is redundant for a specific task.

Author Biographies

Ірина Яківна Зеленьова, Zaporizhzhia Polytechnic National University

Ph.D. of Science, docent, assistant professor of the Department of computer systems and networks

Тетяна Василівна Голуб, Zaporizhzhia Polytechnic National University

assistant of the Department of computer systems and networks

Тетяна Сергіївна Дьячук, Zaporizhzhia Polytechnic National University

assistant of the Department of computer systems and networks

Артем Євгенович Діденко, Zaporizhzhia Polytechnic National University

student of the Department of computer systems and networks

Published
2020-12-24
How to Cite
Зеленьова, І., Голуб, Т., Дьячук, Т., & Діденко, А. (2020). CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA. Electrotechnic and Computer Systems, (33(109), 21-31. https://doi.org/10.15276/eltecs.33.109.2020.3
Section
Computer Systems, Networks and their Components

Most read articles by the same author(s)